Clock signals used in circuits may become corrupted by a multitude of causes and sources resulting in various errors or impairments in the clock signals. The corrupted clock signals may then introduce errors in circuits using the clock signals resulting in degraded circuit performance, errors in the outputs of the circuits, or rendering the circuits inoperable. As an example, corruption of a multi-phase clock signal may manifest as duty-cycle distortion (DCD) as well as skew between the phases of the clock signals constituting the multi-phase clock signal. Sources of corruption may include, for example, process mismatch, temperature fluctuations, differences between the wiring distances of the individual clock signals, improper transistor biasing, or other non-idealities. In particular, when a multi-phase clock must be routed across a significant chip distance or to a large load, it is generally difficult to ensure that the individual clock signals constituting the multi-phase clock arrive at the load with no DCD or skew. DCD and skew degrade circuit performance by reducing the timing margin of circuits that require accurately aligned clock phases. Furthermore, clock errors such as DCD and skew have a greater (more adverse) impact on circuit performance as the clock frequency increases, as a given amount of DCD or skew will occupy a greater fraction of the clock period.
DCD may be defined as the difference between the time duration of a clock signal's “high” pulse and the clock signal's “low” pulse for a given clock cycle. Ideally, and nominally, the high and low pulses have equal duration and hence the DCD is zero. A clock signal having high and low pulses of equal duration is said to have a 50 percent duty cycle. In contrast, a clock signal having high pulses of greater durations than its low pulses may be said to have a duty cycle greater than 50 percent while a clock signal having low pulses of greater durations than its high pulses may be said to have a duty cycle less than 50 percent.
Skew may be defined as the phase error in a desired phase offset (a desired phase offset of 0, 90, 180, or 270 degrees, for example) between two clock signals. As an example, the phase offset between each of the four constituent clock signals of a 4-phase quadrature clock should be 90 degrees; that is, a first one of the clock signals of the 4-phase quadrature clock is nominally taken to have zero degree phase, the second one of the clock signals of the 4-phase quadrature clock should have a 90 degree phase offset relative to the first one of the clock signals, the third one of the clock signals of the 4-phase quadrature clock should have a 90 degree phase offset relative to the second one of the clock signals (and hence a 180 degree phase offset relative to the first one of the clock signals), and the fourth one of the clock signals of the 4-phase quadrature clock should have a 90 degree phase offset relative to the third one of the clock signals (and hence a 270 degree phase offset relative to the first one of the clock signals). Similarly, the phase offset between the two clock signals of a 2-phase differential clock should be 180 degrees. Any discrepancy in these phase offsets is referred to as skew.
Thus, if the clock signal that must be corrected is, for example, a four-phase clock signal, potentially seven impairments may be required to be corrected: the DCD in each of the four constituent clock signals and the skew between each of the three clock signals of non-zero phase relative to the clock signal of nominal zero degree phase. Additionally, it is generally desirable to perform the correction using as few resources, particularly power and chip area, as possible.